The present invention relates to a thin film transistor(TFT) processing, and more particularly to process for forming an ohmic layer by activating dopant impurities using hydrogen ion implantion or doping to provide low resistance ohmic contrast to the source and drain of a TFT.
Thin film transistors(TFTs) are generally used for operating an active matrix liquid crystal display(AMLCD). Up until recently, amorphous silicon(a-Si) has been normally used for forming TFTs in AMLCDs. The field effective mobility of an a-Si TFT, however is much lower than that of crystalline Si TFT, so that poly-Si TFT can be employed for large screen TV panel, note book PC panel and monitor panel with integrated driver circuits. Since driver integrated circuit can be formed on the LCD panel, the number of the connections between the driver IC and other pixel elements can be minimized. Thus, a more efficient and economic LCD panel can be obtained. For integrated circuit, CMOS circuit is necessary since it gives the simple circuit design and high speed driving.
In the p-Si TFT, however, glass is employed as a substrate, accordingly, various process steps used to fabricated the p-Si TFT must be carried out at temperatures below 600.degree. C., which is lower than a softening point of glass. In particular, both formation of the channel layer and activation of source/drain implanted regions must be performed at these relatively low temperatures.
After introducing dopants into the p-Si, two methods of the ohmic layer have been proposed so far. These are thermal activation and laser activation. When thermal activation method is applied, low cost glass substrates typically warp because the activation process is carried out above 600.degree. C., which is higher than softening point of glass. On the other hand, when laser activation method is applied, also, the date electrodes including Al, Ta, or Cr can be damaged by the laser beam, so that the gate electrode must be formed of a metal resistant to the laser light, such as polysilicon. Polysilicon, however, has relative high electrical resistivity.
FIG. 1 is a sectional view of conventional p-Si CMOS TFT. In figure, a NMOS and a PMOS TFTs are fabricated in parts A and B of the substrate 1, respectively. A buffer layer 2, channel regions 3A or 3B, an N-type source and drain regions 4, and P-type source and drain regions 5, which are formed of p-Si, and a gate insulating layer 6 are formed successively on glass substrate 1. Here, N-type source and drain regions 4 are formed in part B in which PMOS is fabricated.
The gate insulating layer 6 is coated on the channel regions 3A or 3B, as well as ohmic layers 4 and 5, and the gate electrode 7 is formed on the gate insulating layer 6. An interlayer insulating layer 9 is coated on the gate insulating layer 6 and source-drain contact holes are formed in the interlayer insulating layer 9 and the gate insulating layer 6. Source-drain electrodes 8 are then formed in the contact holes. And, on the above mentioned TFT, a passivation layer 10 is coated.
Hereinafter, the conventional process of fabricating p-Si TFT CMOS will be explained with reference to FIGS. 2A-2E as follows.
The buffer layer 2 and the active layer 3 are deposited on glass substrate 1, as shown in FIG. 2A. The active layer 3 is patterned and then the gate insulating layer 6 is coated on the active layer 3 and the buffer layer 2. Gate metal is then coated and patterned on gate insulating layer 6 to form the gate electrode 7. Thereafter, a photoresist 12 is coated for blocking the P-type transistor of the patterned active layer 3, and N-type dopant doping is then carried out into the p-Si layer 3, as shown in FIG. 2B. Subsequently, P-type dopant doping is carried out after the elimination of the photoresist 12, as shown in FIG. 2C.
Dopants which are doped into the active layer 3 are activated by laser or heat to form the source and drain regions of the N-type and P-type transistors, as shown in FIG.2D. Since the activation temperature must be high enough to form the source and drain regions and the dopants must be activated at temperatures higher than approximate 600.degree. C., there is a possibility that the glass used for substrate may be warpaged or shrinked. Further, if laser activation is used, in addition, typical lasers such as KrF and XeCl eximer laser are employed over the entire surface of the substrate 1, not just the source-drain regions so that the gate electrode 7 can be damaged. For this reason, gate electrode 7 must be made of material highly resistant to laser irradiation.
Thereafter, the interlayer insulating layer 9 is coated and patterned to form the source-drain contact hole. The source-drain electrode 8 is coated in the source-drain contact hole and, lastly, a passivation layer 10 is coated on substrate 1, as shown in FIG.2E.
As noted above, however, glass substrates can be warped it the thermal activation step is carried about at temperatures higher than 600.degree. C. Further, if the laser activation method is used, the gate can only be formed of material unaffected by laser light. Such material, e.g., polysilicon, has relatively high electrical resistance. Low resistance materials typically cannot be used. In addition, to prevent the damage of the photoresist for blocking the P-type and N-type transistors, ion doping must also be carried out at sufficient low temperature.